1. Field of the Invention
Embodiments of the invention generally relate to the fabrication of semiconductor devices and to chemical mechanical polishing and planarization of semiconductor devices.
2. Background of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity for conductors and materials having low dielectric constant (low k, defined herein as having dielectric constants, k, less than about 4.0) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitative coupling between layers can detrimentally affect the functioning of semiconductor devices.
One conductive material gaining acceptance is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 xcexcxcexa9-cm compared to 3.1 xcexcxcexa9-cm for aluminum), a higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, i.e., vias, and horizontal interconnects, i.e., lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or xe2x80x9cpolishingxe2x80x9d a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in dual damascene processes to remove excess deposited material and to provide an even surface for subsequent levels of metallization and processing. Planarization may also be used in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition to effect both chemical activity and mechanical activity.
Conventionally, in polishing copper features, such as a dual damascenes, the copper containing material is polished to the barrier layer, and then the barrier layer is polished to the underlying dielectric layer. However, the interface between copper and the barrier layer is generally non-planar and the copper material and the barrier materials are often removed from the substrate surface at different rates, both of which contribute to the retention of copper containing material, or residue, on the surface of the substrate during copper removal processes. To ensure removal of all the copper material and residue before removing the barrier material, it is necessary to overpolish the copper and the interface. Overpolishing of copper and the interface can result in forming topographical defects, such as concavities or depressions, referred to as dishing, and can further lead to non-uniform removal of the barrier layer disposed thereunder. Overpolishing may also result in scratching of materials on the substrate surface, such as the barrier material or a dielectric material.
FIG. 1 is a schematic view of a substrate illustrating the phenomenon of dishing. Conductive lines 11 and 12 are formed by depositing conductive materials, such as copper or copper alloy, in a feature definition formed in the dielectric layer 10, typically comprised of silicon oxides or other dielectric materials. After planarization, a portion of the conductive material is depressed by an amount D, referred to as the amount of dishing, forming a concave copper surface. Dishing results in a non-planar surface that impairs the ability to print high resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device formation. Dishing also detrimentally affects the performance of devices by lowering the conductance and increasing the resistance of the devices, contrary to the benefit of using higher conductive materials, such as copper.
One solution to limit dishing is to remove copper material from the substrate surface in two sequential polishing steps. For example, the first step comprises using an abrasive containing slurry on a conventional polishing pad to remove the bulk copper and then using a second abrasive containing slurry to remove the remaining copper and which may also remove a portion of the barrier layer. However, this two-step xe2x80x9cslurryxe2x80x94slurryxe2x80x9d technique can still result in an unacceptable amount of dishing. Slurry polishing has also been observed to form scratches in the surface of the substrate. The presence of scratches can detrimentally affect polishing uniformity and can detrimentally affect subsequent polishing.
Additionally, two-step copper polishing by most conventional processes require removal of the bulk copper to be performed on a first platen and the removal of the remaining copper to be performed on a second platen. The removal of the bulk copper material is a lengthy process compared to the remaining copper removal step, and the bulk copper removal becomes a limiting step that negatively effects throughput of a polishing system.
Therefore, there exists a need for apparatus and methods that facilitate the removal of copper containing material from the surface of a substrate with minimal or reduced dishing and scratching of the substrate surface.
The invention generally provides an apparatus and method for planarizing a substrate surface by the use of one or more hard polishing pads while reducing dishing and minimizing scratching of the substrate surface. In one aspect, a system is provided for processing substrates including a first platen adapted for polishing a substrate with a hard polishing pad disposed thereon, a second platen adapted for polishing a substrate with a hard polishing pad disposed on the second platen, a third platen adapted for polishing a substrate with a hard polishing pad disposed on the third platen, and a computer based controller configured to cause the system to perform a method comprising polishing the substrate with a first hard polishing pad on a first platen, polishing the substrate with a second hard polishing pad on a second platen, and then polishing the substrate with a third hard polishing pad on a third platen. The system may further comprise a carousel, at least two substrate head assemblies suspended from the carousel and capable of holding a substrate thereon, and a positioning member coupled to the carousel to move the carousel and position the substrate head assemblies over a selected polishing platen.
In another aspect, a method is provided for planarizing a substrate surface including polishing the substrate with a first hard polishing pad on a first platen to substantially remove bulk copper containing materials formed on a substrate surface, polishing the substrate with a second hard polishing pad on a second platen to remove residual copper containing materials, and then polishing the substrate with a third hard polishing pad on a third platen to remove a barrier layer formed on the substrate surface.
In another aspect, a method is provided for planarizing a substrate surface including providing a substrate comprising a dielectric layer with feature definitions formed therein, a barrier layer conformally deposited on the dielectric layer and in the feature definitions formed therein, and bulk copper containing material deposited on the barrier layer and filling the feature definitions formed therein, chemical mechanical polishing the substrate with a first hard polishing pad until the bulk copper containing material is substantially planarized, chemical mechanical polishing the substrate with a second hard polishing pad to remove residual copper containing materials formed thereon, and then chemical mechanical polishing the substrate with a third hard polishing pad to remove the barrier layer above the dielectric layer.
In another aspect, a computer readable medium is provided bearing instructions for planarizing a substrate surface, the instructions arranged such that when executed by one or more processors, cause one or more processors to control a chemical mechanical polishing system to polish the substrate with a first hard polishing pad on a first platen to substantially remove bulk copper containing materials formed on a substrate surface, polish the substrate with a second hard polishing pad on a second platen to remove residual copper containing materials, and then polish the substrate with a third hard polishing pad on a third platen to remove a barrier layer formed on the substrate surface.